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[VHDL-FPGA-Verilog] ad9777的测试程序，对SPI进行初始化，运用ISE环境，成功地进行综合和实现.rar

Description: ad9777的测试程序，对SPI进行初始化，运用ISE环境，成功地进行综合和实现
Platform: | Size: 2664973 | Author: Ariesl | Hits:

[VHDL-FPGA-Verilog] SPI串口的内核实现spicore

Description: SPI串口的内核实现spicore SPI串口的内核实现spicore-SPI string mouth essence realizes spicore the SPI string mouth essence to realize spicore the SPI string mouth essence to realize spicore
Platform: | Size: 6144 | Author: lfq | Hits:

[VHDL-FPGA-Verilog] SPI_Code(Verilog)

Description: SPI总线硬件描述语言Verilog下的实现，含主模式和从模式的实现，经过仿真验证，可作为一个单独的模块使用-SPI bus under the Verilog hardware description language to achieve with the main mode and slave mode realization, through simulation, can be used as a separate module uses
Platform: | Size: 5120 | Author: 高兵 | Hits:

[VHDL-FPGA-Verilog] spi.tar

Description: SPI(serial port interface)的Verilog/VHDL源代碼，已模擬並驗證。-SPI (serial port interface) of the Verilog/VHDL source code, has been simulated and verified.
Platform: | Size: 116736 | Author: hcjian | Hits:

[Windows CE] wince+spi

Description: verilog vcspi file with testbench
Platform: | Size: 1944576 | Author: xgh | Hits:

[SCM] mcu-cpld-spi

Description: mcu与cpld之间spi接口程序，mcu为master，cpld用verilog写成slave模块-mcu with spi interface program between the CPLD, mcu for the master, cpld written using Verilog slave module
Platform: | Size: 110592 | Author: 叶灿 | Hits:

[ARM-PowerPC-ColdFire-MIPS] ssp_arm

Description: arm 的ssp—spi verilog源代码-arm of the ssp-spi verilog source code
Platform: | Size: 819200 | Author: 子墨 | Hits:

[VHDL-FPGA-Verilog] SPI

Description: Verilog SPI 源码（来自网络）-Verilog SPI
Platform: | Size: 49152 | Author: lanbow | Hits:

[Other] spi.tar

Description: This is a verilog code used oversampled clock to implement SPI slave. Also include C code for a ARM processor as the SPI master-This is a verilog code used oversampled clock to implement SPI slave
Platform: | Size: 1024 | Author: johnl | Hits:

[VHDL-FPGA-Verilog] spi

Description: SPI Verilog code with programmable clock
Platform: | Size: 5455872 | Author: sudhir | Hits:

[Other] rtl

Description: SPI verilog RTL code
Platform: | Size: 5120 | Author: china | Hits:

[Program doc] SPI-in-Verilog-implementation

Description: SPI的Verilog实现(非常的全面和详细，还带有SPI算法的注解).-SPI in Verilog implementation (a very full and detailed, but also with the SPI algorithm annotation).
Platform: | Size: 8192 | Author: 尚林 | Hits:

[VHDL-FPGA-Verilog] spi

Description: SPI IP CORE Verilog quartus-SPI IP CORE Verilog quartusii
Platform: | Size: 1487872 | Author: thegreeneyes | Hits:

[VHDL-FPGA-Verilog] SPI

Description: SPI verilog 代码 有代码和TB 以及文件说明-SPI verilog
Platform: | Size: 16384 | Author: wuming | Hits:

[VHDL-FPGA-Verilog] spi

Description: Verilog语言写的SPI接口（层次化设计，便于升级）-The implememt of SPI interface using Verilog HDL
Platform: | Size: 43008 | Author: guorui | Hits:

[VHDL-FPGA-Verilog] verilog-SPI-core

Description: 用VerilogHDL写的spi 核的例子-A simple example of SPI core using Verilog HDL
Platform: | Size: 49152 | Author: guorui | Hits:

[VHDL-FPGA-Verilog] QUAD-SPI-verilog

Description: 难得的SPI NOR Flash控制器Verilog源代码，支持四路串行通道！-Rare SPI NOR Flash controller Verilog source code, supports four serial channels!
Platform: | Size: 110592 | Author: david | Hits:

[VHDL-FPGA-Verilog] Nitro-Parts-lib-SPI-master

Description: Nitro-Parts-lib-SPI Verilog SPI master and slave
Platform: | Size: 5120 | Author: d.pershin | Hits:

[Embeded-SCM Develop] SPI

Description: SPI（Serial Peripheral Interface，串行外设接口）是Motorola公司提出的一种同步串行数据传输标准，是一种高速的，全双工，同步的通信总线，在很多器件中被广泛应用。 SPI相关缩写 SS: Slave Select，选中从设备，片选。 CKPOL (Clock Polarity) = CPOL = POL = Polarity = （时钟）极性 CKPHA (Clock Phase) = CPHA = PHA = Phase = （时钟）相位 SCK = SCLK = SCL = SPI的时钟（Serial Clock） Edge = 边沿，即时钟电平变化的时刻，即上升沿(rising edge)或者下降沿(falling edge)。 对于一个时钟周期内，有两个edge，分别称为： Leading edge = 前一个边沿 = 第一个边沿，对于开始电压是1，那么就是1变成0的时候，对于开始电压是0，那么就是0变成1的时候； Trailing edge = 后一个边沿 = 第二个边沿，对于开始电压是1，那么就是0变成1的时候（即在第一次1变成0之后，才可能有后面的0变成1），对于开始电压是0，那么就是1变成0的时候；(SPI (Serial Peripheral Interface, serial peripheral interface) is a synchronous serial data transmission standard put forward by Motorola company, is a high-speed, full duplex, synchronous communication bus, is widely used in many devices. SPI related abbreviations SS: Slave Select, selected from the device, chip select. CKPOL (Clock, Polarity) = CPOL = POL = Polarity = (clock) polarity CKPHA (Clock, Phase) = CPHA = PHA = Phase = (clock) phase SCK = SCLK = SCL = SPI clock (Serial, Clock) Edge = edge, instant clock, level change time, i.e. rising edge (rising, edge) or falling edge (falling, edge). For a clock cycle, there are two edge, respectively: Leading edge = front edge = first edge, for start voltage is 1, then 1 is 0, for start voltage is 0, then 0 is 1; Trailing = edge = second after an edge edge, the start voltage is 1, it is 0 to 1 of the time (that is, after the first 1 to 0, it may be behind the 0 to 1), the start voltage is 0, it is 1 to 0 times;)
Platform: | Size: 6144 | Author: helimpopo | Hits:

[Other] SD SPI模式verilog外加modelsim仿真结果

Description: SD卡的SPI模式verilog代码，外加modelsim仿真结果。(SD card's SPI mode Verilog code, plus the simulation results of modelsim.)
Platform: | Size: 59392 | Author: qwer.123 | Hits:
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